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八位的伪随机数产生的verilog文件
- 八位的伪随机数产生的verilog文件linear-feedback-shift-register-eight pseudo-random number generator in Verilog document linear-feedback - shift-register
Verilog-HDL
- 本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。 -the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples w
sWave.rar
- 正弦波，Verilog波形发生器，很好的东西,Sine wave, Verilog waveform generator, a good thing
EPM240_SCH_and_program.rar
- EPM240 cpld 原理图+程序。 Verilog HDL语言。 程序有正弦波发生器，ADC0804直流采样和显示，汉字滚动，交通灯，键盘，显示程序，计数器等等。,Schematic diagram+ EPM240 cpld procedures. Sine wave generator procedures, ADC0804 DC sampling and showed that Chinese scroll, traffic lights, keyboard, display pro
pn_generator.rar
- FPGA实现pn发生器，Verilog代码实现，另带modlesim的仿真测试文件，很有价值。,FPGA realization of pn generator, Verilog code, and the other with the simulation test modlesim documents of great value.
dual_ram
- FPGA和双端口RAM的DDS任意波形发生器的实现-FPGA and dual-port RAM of the DDS Arbitrary Waveform Generator
PWM256
- Verilog 所寫的可程式 PWM 信號產生器. 特點是設定參數時不會產生Glitch現象. 包含二個 .do 檔給 model*sim 幫助編譯及模擬.-A PWM generator writing in Verilog. This module will generate glitch while changing the setting. Including 2 .do files which can help compiling and simulating in the model
FPGA_Clk
- 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。 使用计时器的方式产生时钟波形。 提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other
dds
- 基于FPGA的双路可移相任意波形发生器 Altera中国大学生电子设计文章竞赛获奖作品刊登-FPGA-based dual phase shifter can be arbitrary waveform generator Altera China Undergraduate Electronic Design Contest winning entries published articles
FPGAdezizhixingSPWMboChengXu
- 基于FPGA的自治型SPWM波形发生器的设计！正弦脉宽调制（SPWM）技术在以电压源逆变电路为核心的电力电子装置中有着广泛的应用，如何产生SPWM脉冲序列及其实现手段是PWM技术的关键。大家共同探讨哈！-FPGA based SPWM autonomy-based waveform generator design! Sinusoidal pulse width modulation (SPWM) technology in the voltage source inverter circuit
sgs32
- Verlog HDL 写得一款32路方波发生器，例子是4路可以自己加，相位可调，频率可调，占空比可调。具体参见readme.doc.此处只提供了源码包含顶层模块sgs32.v 子模块dds.v和pll设置模块altp.v及波形驱动文件-Verlog HDL write a 32 square-wave generator, for example, is able to add 4-way, phase adjustable, adjustable frequency, adjustable d
DDS
- 基于DDS技术的函数波形发生器设计，适合用fpga设计波形发生器用-Based on DDS technology function waveform generator design, suitable for FPGA design with Waveform Generator
matlab
- 开题报告哦啊 我精心设计的 希望大家喜欢 任意波形发生器-Oh ah problem that the report carefully designed my hope that everyone likes Arbitrary Waveform Generator
FPGA_NEW_APPROACH_TO_IMPLEMENT_CHAOTIC_GENERATOR.
- In this paper, a new method is introduced to implement chaotic generators based on the Henon map and Lorenz chaotic generators given by the state equations using the Field Programmable Gate Array (FPGA). The aim of this method is to increase the freq
whole
- 用AT89C51实现的数控电压源，电流源，波形发生器-digital voltage source,current source,wave generator,using AT89C51
transfer
- 基于CPLD的PWM波形的发生器，编程语言为verilog,开发环境为QuartusII.-The CPLD-based PWM waveform generator, the programming language to verilog, development environment for QuartusII.
c_xapp260
- xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Gen
Clock_generator
- Verilog source code for a clock generator
clock_generator
- clock generator verilog代码，供大家参考-clock generator verilog code for your reference
verilog状态机
- 采用Verilog语言设计一个序列信号发生器和一个序列信号检测器，二者都以状态机模式实现。序列信号发生器输出8位宽度的序列信号“10110110”，通过数码管显示出来；序列信号发生器的输出接入序列信号检测器，检测器检测当前的输入信号，若出现目标序列信号则通过蜂鸣器输出一个声响，表示检测到有效的目标信号。(A sequence signal generator and a sequence signal detector are designed using Verilog language, b